Deciding Disputes: Factors That Guide Chinese Courts in the Adjudication of Rural Responsibility Contract Disputes

Post-silicon validation and debug, or ensuring that software executes correctly on the silicon of a multi-processor system-on-chip (MPSOC) is complicated, as it involves checking global properties that are distributed on the chip. In this paper we define an architecture to non-intrusively observe global properties at run time using distributed monitors. The architecture enables to perform actions when a property holds, such as stopping (part of) the system for inspection. We apply this architecture to the problem of software races that result in incorrect communication between concurrent tasks on different processors. In a case study, where we implemented monitors, event distribution, and instruments to stop communication between intellectual property (IP) blocks, we demonstrate that these races can be detected and classified as timing violations or as FIFO protocol violations.©2010 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. Erik Larsson, Bart Vermeulen and Kees Goossens, A Distributed Architecture to Check Global Properties for Post-Silicon Debug, 2010, IEEE European Test Symposium (ETS'10), Prague, Czech Republic, May 24-28, 2010.</p

Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip

A Network on Chip (NoC) with end-to-end flow control is modelled by a cyclo-static dataflow graph. Using the proposed model together with state-of-the-art dataflow analysis algorithms, we size the buffers in the network interfaces. We show, for a range of NoC designs, that buffer sizes are determined with a run time comparable to existing analytical methods, and results comparable to exhaustive simulation

Process-variation aware mapping of real-time streaming applications to MPSoCs for improved yield

Abstract—As technology scales, the impact of process variation on the maximum supported frequency (FMAX) of individual cores in a MPSoC becomes more pronounced. Task allocation without variation-aware performance analysis can result in a significant loss in yield, defined as the number of manufactured chips satisfying the application timing requirement. We propose variation-aware task allocation for real-time streaming applica-tions modeled as task graphs. Our solutions are primarily based on the throughput requirement, which is the most important timing requirement in many real-time streaming applications. The three main contributions of this paper are: 1) Using data flow graphs that are well-suited for modeling and analysis of real-time streaming applications, we explicitly model task execution both in terms of clock cycles (which is independent of variation) and seconds (which does depend on the variation of the resource), which we connect by an explicit binding. 2) We present two approaches for optimizing the yield. The approaches give different results at different costs. 3) We present exhaustive and heuristic algorithms that implement the optimization approaches. Our variation-aware mapping algorithms are tested on models of real applications, and are compared to the mapping methods that are unaware of hardware variation. Our results demonstrate yield improvements of up to 50 % with an average of 31%, showing the effectiveness of our approaches. Index Terms—Process variation, Multiprocessor System-on

Slack Exploitation for Aggressive Dynamic Power Reduction in SoC

The increasing power consumption of today’s system-on-chip (SoC) outpaces the trend of increasing battery capacity. The applications offered to customers grow tremendously too, a trend that is accelerating in the future. This yields stronger requirements for lower power consumption. During design, a system is dimensioned to worst-case workload requirements. Most of the time, workload is far below this level, which results in slack in some parts of the system. Our idea is to exploit this available slack by using adequate variants of dynamic voltage and frequency scaling and power gating. For scalability reasons, we commence our research with local dynamic adaptive power and frequency scaling, based on the slack observed at run time. This paper presents the motivations and possible directions for our research

NPTSN:RL-Based Network Planning with Guaranteed Reliability for In-Vehicle TSSDN

To achieve strict reliability goals with lower redundancy cost, Time-Sensitive Software-Defined Networking (TSSDN) enables run-time recovery for future in-vehicle networks. While the recovery mechanisms rely on network planning to establish reliability guarantees, existing network planning solutions are not suitable for TSSDN due to its domain-specific scheduling and reliability concerns. The sparse solution space and expensive reliability verification further complicate the problem. We propose NPTSN, a TSSDN planning solution based on deep Reinforcement Learning (RL). It represents the domain-specific concerns with the RL environment and constructs solutions with an intelligent network generator. The network generator iteratively proposes TSSDN solutions based on a failure analysis and trains a decision-making neural network using a modified actor-critic algorithm. Extensive performance evaluations show that NPTSN guarantees reliability for more test cases and shortens the decision trajectory compared to state-of-the-art solutions. It reduces the network cost by up to 6.8x in the performed experiments

Decentralized Configuration of TSCH-Based IoT Networks for Distinctive QoS:A Deep Reinforcement Learning Approach

The IEEE 802.15.4 Time-Slotted Channel Hopping (TSCH) is widely used as a reliable, low-power, and low-cost communication technology for many industrial Internet-of-Things (IoT) networks. In many applications, Quality-of-Service (QoS) requirements are different for heterogeneous nodes, necessitating non-equal parameter settings per node. This results in a very large configuration space making space exploration complex and time-consuming. Moreover, network state and QoS requirements may change over time. Thus, run-time configuration mechanisms are needed for making decisions about proper node settings to consistently satisfy diverse and dynamic QoS requirements. In this paper, we propose a run-time decentralized self-optimization framework based on Deep Reinforcement Learning (DRL) for parameter configuration of a multi-hop TSCH network. DRL adopts neural networks as approximate functions to speed up the process of converging to QoS-satisfying configurations. Simulation results show that our proposed framework enables the network to use the right configuration settings according to the diverse QoS demands of different nodes. Moreover, it is shown that the convergence time of the learning framework is in the order of a few minutes which is acceptable for many IoT applications

Multi-Factor Pruning for Recursive Projection-Aggregation Decoding of RM Codes

The recently introduced recursive projection aggregation (RPA) decoding method for Reed-Muller (RM) codes can achieve near-maximum likelihood (ML) decoding performance. However, its high computational complexity makes its implementation challenging for time- and resource-critical applications. In this work, we present a complexity reduction technique called multi-factor pruning that reduces the computational complexity of RPA significantly. Our simulation results show that the proposed pruning approach with appropriately selected factors can reduce the complexity of RPA by up to $92\%$ for $\text{RM}(8,3)$ while keeping the comparable error-correcting performance

Hardware Implementation of Iterative Projection-Aggregation Decoding of Reed-Muller Codes

In this work, we present a simplification and a corresponding hardware architecture for hard-decision recursive projection-aggregation (RPA) decoding of Reed-Muller (RM) codes. In particular, we transform the recursive structure of RPA decoding into a simpler and iterative structure with minimal error-correction degradation. Our simulation results for RM(7,3) show that the proposed simplification has a small error-correcting performance degradation (0.005 in terms of channel crossover probability) while reducing the average number of computations by up to 40%. In addition, we describe the first fully parallel hardware architecture for simplified RPA decoding. We present FPGA implementation results for an RM(6,3) code on a Xilinx Virtex-7 FPGA showing that our proposed architecture achieves a throughput of 171 Mbps at a frequency of 80 MHz

An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration

In this paper we present a network interface for an on-chip network. Our network interface decouples computation from communication by offering a shared-memory abstraction, which is independent of the network implementation. We use a transactionbased protocol to achieve backward compatibility with existing bus protocols such as AXI, OCP and DTL. Our network interface has a modular architecture, which allows flexible instantiation. It provides both guaranteed and best-effort services via connections. These are configured via network interface ports using the network itself, instead of a separate control interconnect. An example instance of this network interface with 4 ports has an area of 0.143mm in a 0.13m technology, and runs at 500 MHz